1. Field of the Invention
The invention described in the present specification relates to a general-purpose buffer circuit formed on an insulating substrate using single-channel type thin film transistors. It should be noted that the buffer circuit according to the present invention is not limited to any specific application, but is applicable to a variety of applications, devices and products. Incidentally, the invention described in the present specification has aspects of a semiconductor device, display panel and electronic equipment.
2. Description of the Related Art
The low-temperature poly-silicon (LTPS) process can form circuits using both n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) thin film transistors (TFTs). In the LTPS process, therefore, it is common to manufacture circuits so-called CMOS (complementary metal oxide semiconductor) circuits, using these two types of thin film transistors.
On the other hand, CMOS circuits inevitably lead to an increase in the number of process steps because of the two types of thin film transistors used. This increase in the number of process steps results in reduced production efficiency, thus contributing to increased manufacturing cost.
Therefore, even if the poly-silicon process is used, circuits identical in function to CMOS circuits should preferably be achieved using only single-channel type (NMOS or PMOS) thin film transistors.
Moreover, single channel type circuits of this sort are applicable when circuits are formed with amorphous silicon or organic semiconductors.
In the case of amorphous silicon, for example, NMOS thin film transistors are the only choice to manufacture circuits. In the case of organic TFTs, PMOS thin film transistors are the only choice to manufacture circuits.
Against this backdrop, circuits identical in function to CMOS circuits should preferably be achieved using only single-channel type (NMOS or PMOS) thin film transistors.
The present specification focuses its attention on a buffer circuit. A buffer circuit is, needless to say, a general-purpose circuit incorporated in a variety of circuits. Therefore, a buffer circuit is basically not limited to any specific application. It should be noted, however, that, in the description given below, we assume for the sake of convenience that a buffer circuit is used in a drive circuit adapted to drive a display panel.
In the following description, an existing example of a buffer circuit will be described in relation to an active-matrix-driven organic EL (electroluminescence) panel.
FIG. 1 illustrates a system configuration example of an organic EL panel. An organic EL panel 1 illustrated in FIG. 1 includes a pixel array section 3, signal line drive section 5, first control line drive section 7 and second control line drive section 9. These components are arranged on a panel substrate.
The pixel array section 3 has subpixels 11 arranged in a matrix form according to the display resolution. FIGS. 2 and 3 illustrate equivalent circuit examples of the subpixel 11. It should be noted that the subpixels 11 shown in FIGS. 2 and 3 both include only NMOS thin film transistors.
In the two figures, reference numeral N1 denotes a sampling transistor, N2 a drive transistor, N3 a lighting control transistor, and Cs a holding capacitor. Further, reference numeral WSL corresponds to a write control line, and LSL a lighting control line.
Incidentally, FIG. 2 corresponds to a circuit configuration when an organic EL element OLED is lit up or extinguished by turning the lighting control transistor T3 on or off as a driving method.
On the other hand, FIG. 3 corresponds to a circuit configuration when the organic EL element OLED is lit or extinguished by changing the potential of the lighting control line LSL as a driving method. It should be noted that, in the case of FIG. 3, the lighting control line LSL serves also as a current supply line.
FIGS. 4A to 4C illustrate a timing diagram when a signal potential Vsig (Data) is written to the subpixel 11 shown in FIGS. 2 and 3. Incidentally, FIG. 4A illustrates the driving waveform of a signal line DTL. The signal line DTL is supplied with the signal potential Vsig associated with the pixel gray level Data. The magnitude of the drive current supplied by the drive transistor N2 is determined by the magnitude of the signal potential Vsig here. The organic EL element OLED is a current-driven element. The larger the drive current here, the higher the luminance.
FIG. 4B illustrates the driving waveform of the write control line WSL. While the same line WSL is at high level, the sampling transistor N1 turns on, causing the potential of the signal line DTL to be written to the gate electrode of the drive transistor N2.
FIG. 4C illustrates the driving waveform of the lighting control line LSL. The lighting control line LSL is driven by two values or high and low levels. This switching of the potential permits the organic EL element OLED to be lit or extinguished.
It should be noted that the subpixel 11 shown in FIG. 2 and that in FIG. 3 differ from each other in control amplitude of the lighting control line LSL. In the case of FIG. 2, the lighting control line LSL need only drive the drive transistor N2. In contrast, in the case of FIG. 3, the lighting control line LSL must supply an operating voltage to the drive transistor N2 and organic EL element OLED.
As illustrated in FIGS. 4A to 4C, after the writing of the signal potential Vsig, the organic EL element OLED is lit when the lighting control line LSL is at high level, and unlit when the same line LSL is at low level.
It should be noted that the peak luminance level can be controlled by variably controlling the ratio of the lighting period length (Duty) to one field period.
In addition to the above, the lighting control line LSL shown in FIG. 4C is also used to adjust the motion image characteristics. To adjust the motion image characteristics, the number of times of lighting and lighting period timings per field period must be adjusted.
Therefore, a plurality of different types of pulses must be output to the second control line drive section 9.
Moreover, in the case of the line sequential writing scheme common to active matrix driving, it must be possible to shift these pulse waveforms sequentially on a line-by-line basis.
That is, this type of control line drive section must be able to serve two purposes, i.e., setting the lengths of the control pulses as desired and sequentially shifting the pulses to the next stage on a line-by-line basis.
In the case of the subpixel 11 shown in FIGS. 2 and 3, the threshold and mobility corrections of the drive transistor N2 may be necessary during the writing of the signal potential Vsig. FIGS. 5A to 5F illustrate a timing diagram of the subpixel 11 associated with FIG. 2. Incidentally, if the subpixel 11 shown in FIG. 2 has the correction capabilities, a current supply line PSL is driven as illustrated in FIG. 5C. Further, FIGS. 6A to 6E illustrate a timing diagram of the subpixel 11 associated with FIG. 3. It should be noted that the subpixels 11 shown in FIGS. 2 and 3 differ from each other in that the initialization and lighting period control are performed separately in one of the subpixels 11 and not in another.
The lighting period control must vary the ratio between lighting and non-lighting periods (Duty) to adjust the peak luminance. Further, the lighting period control must change the number of times lighting and non-lighting periods are switched per field period to adjust the motion image characteristics. It is for these purposes that the circuit configuration of the second control line drive section 9 is generally complicated.
Therefore, the circuit configuration shown in FIG. 2 is advantageous in providing a simple control interface because separate supply lines are provided for the initialization pulse adapted to control the timings at which to shift the output pulses and the lighting period control pulse. It should be noted, however, that this circuit configuration requires three control lines, i.e., the write control line WSL, lighting control line LSL and current supply line PSL, as illustrated in FIG. 2.
A description will be given below of not only the threshold and mobility correction operations but also the control operations of the subpixel 11 including the lighting period control for the pixel circuit shown in FIG. 3. Therefore, FIGS. 6A to 6E will be referred to for the description.
It should be noted that the control operations of the pixel circuit shown in FIG. 2 are the same as those of the pixel circuit shown in FIG. 3 except that the initialization and lighting period control are performed separately. Therefore, the description thereof will be omitted.
FIG. 6A illustrates the driving waveform of the write control line WSL. For example, while the same line WSL is at high level, the sampling transistor N1 turns on, causing the potential of the signal line DTL to be written to the gate electrode of the drive transistor N2.
It should be noted that the first high level period in the FIG. 6A is used to correct the variation of a threshold potential Vth of the drive transistor N2.
On the other hand, the second high level period in FIG. 6A is used not only to write the signal potential Vsig commensurate with the pixel gray level but also to correct the variation of a mobility u of the drive transistor N2. Incidentally, the trailing edge of the second high level period falls diagonally so as to set the optimal mobility correction period for all gray levels from high luminance level (high signal potential) to low luminance level (low signal potential).
The term “mobility correction” refers to the operation adapted to correct the difference in mobility between the different drive transistors N2, some with the high mobility u and others with the low mobility μ. In principle, the lower the luminance (the signal potential), the longer the correction period.
FIG. 6B illustrates the driving waveform of the signal line DTL. Two different potentials are applied to the same line DTL. An offset voltage Vofs is adapted to correct the threshold of the drive transistor N2. The signal potential Vsig supplies a pixel gray level. The magnitude of the drive current supplied by the drive transistor N2 is determined by the magnitude of the signal potential Vsig here. The organic EL element OLED is a current-driven element. The larger the drive current here, the higher the luminance.
FIG. 6C is the driving waveform of the lighting control line LSL. The lighting control line LSL is driven by two values or high and low levels. The first low level period shown in FIG. 6C is used to provide an initialization period. The second low level period shown in FIG. 6C is used to provide a non-lighting period after the start of light emission.
The initialization here is adapted to spread a gate-to-source voltage Vgs of the drive transistor N2 wider than the threshold voltage Vth. This operation is absolutely essential before the threshold correction and will be hereinafter referred to as the correction preparation operation.
After this correction preparation operation, the offset voltage Vofs is applied to the gate electrode of the drive transistor N2. At the same time, the lighting control line LSL changes to high level. This potential-related operation is the threshold correction operation. After the start of the threshold correction operation, a source potential Vs of the drive transistor N2 increases gradually. The same potential Vs stops increasing when the gate-to-source voltage Vgs of the drive transistor N2 reaches the threshold voltage Vth.
It should be noted that the end of the writing of the signal potential Vsig is followed by the start of a lighting period which lasts until the next writing period. During the lighting period, the organic EL element OLED is lit when the lighting control line LSL is at high level. The same element OLED is unlit when the lighting control line LSL is at low level. The peak luminance level can be controlled by variably controlling the ratio of the lighting period length to one field period.
FIG. 6D illustrates a potential Vg appearing at the gate electrode of the drive transistor N2. FIG. 6E illustrates the potential Vs appearing at the source electrode of the drive transistor N2 (anode of the organic EL element OLED).
As described earlier, the pulses of the write control signal (FIG. 6A) and lighting control signal (FIG. 6C) must vary in length depending on the purpose of driving operation.
In the case of the former, for example, the pulse must vary in length between the threshold correction operation and the signal writing and mobility correction operation. On the other hand, in the case of the latter, the pulse must vary in length between the correction preparation operation and the lighting/extinguishing control of the organic EL element OLED during a lighting period.
Therefore, the first and second control line drive sections 7 and 9 must be able to each produce pulse outputs in a plurality of different lengths. Moreover, in the case of the line sequential writing scheme common to active matrix driving, it must be possible to shift these pulse waveforms sequentially on a line-by-line basis. That is, this type of control line drive section must be able to serve two purposes, i.e., setting the lengths of the control pulses as desired and sequentially shifting the pulses to the next stage on a line-by-line basis.
FIGS. 7 to 14F illustrate examples of a control line drive circuit satisfying the above-described driving conditions together with driving examples. It should be noted that the control line drive circuit includes a shift register.
The shift register shown in FIG. 7 includes 2N register stages SR(1) to SR(2N) which are cascaded. The shift register operates in such a manner that each of the stages uses the output pulses of the previous and subsequent stages as drive pulses so as to output, as an output pulse, the clock signal which is fed to the stage.
FIGS. 8A to 8I illustrate drive pulse waveforms of the shift register. It should be noted that FIGS. 8A to 8I illustrate the pulse waveforms when the shift register includes only NMOS thin film transistors.
FIG. 8A illustrates a start pulse ‘st’ adapted to drive the first register stage. FIG. 8B illustrates an end pulse ‘end’ adapted to drive the 2N register stage. FIG. 8C illustrates a clock signal ‘ck1’ for the even-numbered register stages.
FIG. 8D illustrates a clock signal ‘ck2’ for the odd-numbered register stages. FIG. 8E illustrates an output pulse ‘o1’ of the first register stage SR(1). FIG. 8F illustrates an output pulse ‘o(k−1)’ of the k−1th register stage SR(k−1). FIGS. 8G to 8I illustrate output pulses ‘o’ of the respective register stages shown in the figures.
FIG. 9 illustrates an example of the internal circuit of the kth register stage SR. As illustrated in FIG. 9, the thin film transistors making up the register SR are all NMOS transistors. The output stage of this register stage SR includes NMOS thin film transistors N11 and N12 connected in series between a source potential VSS and clock input terminal. It should be noted that the connection midpoint of the thin film transistors N11 and N12 is connected to the output node. Further, a supplementary capacitor Cb1 is connected between the gate electrode of the thin film transistor N11 and the source potential VSS. On the other hand, a supplementary capacitor Cb2 is connected between the gate electrode of the thin film transistor N12 and the clock input terminal. This supplementary capacitor Cb2 supplements the bootstrapping action.
FIGS. 10A to 10F illustrate the relationship in potential between the input and output pulses and nodes A and B which are related to the register stage SR. FIG. 10A illustrates the waveform of a clock signal ‘ck.’ FIG. 10B illustrates the waveform of a first drive pulse ‘in1(k)’ (output pulse ‘out(k−1)’ of the previous register stage). FIG. 10C illustrates the waveform of a second drive pulse ‘in2(k)’ (output pulse ‘out(k+1)’ of the subsequent register stage). FIG. 10D illustrates the waveform of the node B potential (gate potential of the thin film transistor N11). FIG. 10E illustrates the waveform of the node A potential (gate potential of the thin film transistor N12). FIG. 10F illustrates the waveform of an output pulse ‘out’ appearing at the output node.
As illustrated in FIGS. 10A to 10F, the potentials of the nodes A and B change in a complementary manner at the leading edges of the first and second drive pulses ‘in1(k)’ and ‘in2(k).’
This complementary operation is made possible by thin film transistors N13 to N16.
For example, when the first drive pulse ‘in1(k)’ is at high level and the second drive pulse ‘in2(k)’ at low level, the thin film transistors N13 and N14 turn on, and the thin film transistors N15 and N16 turn off. On the other hand, for example, when the first drive pulse ‘in1(k)’ is at low level and the second drive pulse ‘in2(k)’ at high level, the thin film transistors N15 and N16 turn on, and the thin film transistors N13 and N14 turn off.
By the way, while the node A is at high level, the supplementary capacitor Cb2 is charged. Therefore, if the clock signal ‘ck’ changes to high level while the node A is at high level, high level appears in the output pulse ‘out(k).’ As a result, the node A potential increases by the voltage charged in the supplementary capacitor Cb2. At this time, the gate-to-source voltage Vgs of the thin film transistor N12 is equal to the threshold voltage Vth or greater thanks to the bootstrapping action. As a result, the potential of the output pulse ‘out(k)’ presents exactly the same waveform as that of the clock signal ‘ck.’
That is, the shift register shown in FIG. 7 operates in such a manner that the clock signal ‘ck’, extracted in sequential order starting with the first register stage, is output to the output node. In the case of this shift register, therefore, the variable range of the width of the output pulse ‘out’ is limited to one H period (horizontal scan period) during which the clock signal ‘ck’ can vary in width.
It should be noted that this shift register is capable of shifting a plurality of pulse signals within one horizontal period.
FIGS. 11A to 11I illustrate an example of pulse shifting when the clock signal ‘ck’ includes two pulse signals. It should be noted that the waveforms shown in FIGS. 11A to 11I are all associated with those shown in FIGS. 8A to 8I.
Further, FIGS. 12A to 12F illustrate the operation waveforms of the register stage SR associated with the above case. The waveforms shown in FIGS. 12A to 12F are all associated with those shown in FIGS. 10A to 10F. As illustrated in FIG. 12E, both of the two pulse signals are bootstrapped.
Still further, the shift register shown in FIG. 7 can reproduce the same changes in the waveform of the output pulse ‘out’ by adjusting the rise and fall rates of the leading and trailing edges of the clock signal ‘ck.’
FIGS. 13A to 13I illustrate an example of pulse shifting when the trapezoidal clock signal ‘ck’ is fed as the clock signal ‘ck.’ It should be noted that the waveforms shown in FIGS. 13A to 13I are all associated with those shown in FIGS. 8A to 8I.
Still further, FIGS. 14A to 14F illustrate the operation waveforms of the register stage SR associated with the above case. The waveforms shown in FIGS. 14A to 14F are all associated with those shown in FIGS. 10A to 10F. As illustrated in FIG. 14E, the bootstrapping action provides exactly the same trapezoidal waveform as the pulse signal ‘ck.’ This trapezoidal waveform is extracted as the output pulse ‘out.’
The above case is disclosed in Japanese Patent Laid-Open No. 2005-149624